1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices.
2. Description of the Related Art
In a semiconductor device such as a DRAM, a contact plug passing between wirings close to each other is formed by the following process.
First, an electroconductive film is patterned using a silicon nitride film as a mask to form wirings. Then, a silicon nitride film is so formed as to cover the wirings, followed by etching back. As a result, the upper part of the wirings and side walls are covered by the silicon nitride film. Next, an inter-layer insulating film is so formed as to bury the wirings and is flattened. Then, a resist mask is formed by lithography, and dry etching of a high etching selection ratio between the silicon nitride film and the inter-layer insulating film is performed by using this mask to form a contact hole. An electric conductor is buried in this contact hole to form a contact plug in this hole.
This method, known as self-aligned contact (SAC), is in general use. In recent years, however, along with the miniaturization of semiconductor patterns, it has become difficult to satisfy the requirement for a sufficiently high etching selection ratio between the silicon nitride film and the inter-layer insulating film at the time of contact hole formation. Accordingly, it has become difficult to form contact holes by using the SAC technique.
Where a contact hole is to be formed without using the SAC method, a technique in which the contact plug is ensured to be formed not to come into contact with wiring is required. The present inventor has taken note of a technique by which contact holes of a small bore are formed.
By setting the bore of a contact plug arranged between wirings to be set smaller, the allowance of positioning in the process of contact hole formation can be increased. The bore of the contact hole is so set that the contact plug does not come into contact with any one of the wirings even if a displacement, which may occur in the manufacturing process, does occur. Possible causes for such a displacement which may occur in the manufacturing process include a positioning margin for the wirings in lithography, variations in aperture size and variations in the size of the wiring s. For instance where the wiring pitch is 190 nm and the space between wirings is 140 nm, it is desirable for the contact hole bore to be set to no more than 100 nm.
On the other hand, lithography may be carried out by performing superimpose and alignment after a process to fabricate such a minute contact plug. For this reason, in a semiconductor device having a minute contact plug, a large trench of 1 μm or more in width is formed for the aligning purpose.
Thus, in a technique of forming a small-diameter contact plug without using the SAC method, it is required to form patterns extremely unequal in area (contact holes of 100 nm or less in bore and a trench of 1 μm or more in width) on the same semiconductor substrate.
As an example of technique for forming patterns unequal in area, a method by which contact holes differing in diameter are formed is described in Japanese Patent-Laid-Open No. 10-321724 (Patent Document 1). According to this method, together with a self-aligned contact hole, a contact hole larger in bore than that of the self-aligned contact hole is formed. This method will be described below with reference to FIGS. 1A through 1D.
First, a sectional structure shown in FIG. 1A is formed. In this sectional structure, gate electrodes 105G of the memory cell part and first wiring layer 105a of a peripheral circuit part disposed on a p-type silicon substrate 101 are covered by SiN film 107, and further covered by BPSG film 109.
Next, as shown in FIG. 1B, the BPSG film is selectively etched by using a patterned resist mask. Contact hole 111a reaching the substrate by self-aligned contact (SAC) is formed between gate electrodes 105G, and contact hole 111b for first wiring layer 105a is formed in the peripheral circuit part. Where the bore of contact hole 111a is about 0.15 μm, it is described that the bore of contact hole 111b to be about 0.45 μm is desirable.
Then, a doped silicon layer is formed by low pressure CVD. By the formation of this layer, narrow contact hole 111a is filled with the doped silicon layer but wide contact hole 111b for the first wiring layer is not filled with it. Next, as shown in FIG. 1C, the doped silicon layer over the flat part is removed by anisotropic etching. Plug 113 is formed in the contact hole 111a reaching the substrate. Side wall 115 is formed in contact hole 111b for the first wiring layer.
Then, as shown in FIG. 1D, SiN film 107 over first wiring layer 105a is dry-etched and contact hole 111c reaching the first wiring layer is formed in a self-aligned manner.
According to this technique, even if miniaturization by SAC is carried out in the memory cell part, no further step is required to form a contact hole reaching the first wiring layer of the peripheral circuit part.
In the technique described in Patent Document 1, contact holes of different bores are formed. In the example cited above, the contact hole bores are 0.15 μm and 0.45 μm.
Japanese Patent Laid-Open No. 2003-158179 (Patent Document 2) discloses a technique featuring the formation of alignment marks. This technique will be described with reference to FIGS. 2A through 2F.
First, as shown in FIG. 2A, silicon nitride film 202 is formed on the surface of silicon substrate 201, and resist pattern 203 is formed on the film by photolithography.
Then, as shown in FIG. 2B, etching is carried out with resist pattern 203 as a mask, and first mask 202 made up of a silicon nitride film having openings H in the area of trench formation is formed.
Next, a silicon nitride film is formed and patterned by photolithography and etching to form second mask 208 that is so formed as to cover the vicinity of the opening corresponding to the area for alignment mark formation out of openings H. Then, as shown in FIG. 2C, plasma etching is carried out through these second mask 208 and first mask 202 to form trench 204 for element isolation.
Next, second mask 208 is peeled off and removed. Then, a silicon oxide film is formed by CVD so as to fill trench 204 with silicon oxide film 205. At this step, the silicon oxide film is also formed in the area for alignment mark formation where second mask 208 was removed. Then, as shown in FIG. 2D, CMP is performed until the surface of first mask 202 made up of a silicon nitride film is exposed. After that, the silicon oxide film is etched to expose the silicon substrate surface in the area for alignment mark formation.
Next, as shown in FIG. 2E, the silicon substrate is etched to form trench 207 for alignment marks in the area for alignment mark formation.
Next, as shown in FIG. 2F, silicon nitride film 202 is removed to form a flat-surface element-isolated wafer, whose surface has trench 207 for alignment marks.
In order to form a contact plug so as not to come into contact with wirings, it is desirable to restrain the expansion of the bore of the hole relative to the lithographed pattern at the etching step for forming a contact hole. Thus, it is desirable that the etching is to be proceeded vertically to the horizontal plane of the substrate according to the lithographed pattern and that etching in the horizontal direction of the lithographed pattern is to be restrained.
In order to form a small contact hole of 100 nm or less in bore while restraining the expansion of the bore of the hole relative to the lithographed pattern, dry etching is carried out under the following conditions.
Condition 1: A high ratio of selectivity relative to the resist mask
Condition 2: A rich variety of deposition seeds
Desirably, both these conditions may be satisfied.
However, under such conditions, the variety of deposition seeds becomes greater than that of etching seeds in the trench formation part where the area to be etched is large, and the etching is stopped as a consequence. As such, the phenomenon in which the etching rate in the larger area to be etched is lower than that in the smaller area to be etched is referred to as inverse micro loading.
Because of this phenomenon, in order to form small contact holes of 100 nm or less in bore and a trench of 1 μm or more in width to be formed over the same semiconductor substrate by the usual method of lithography, separate lithographic steps for forming resist masks having apertures corresponding the respective sizes have to be carried out. The resultant increase in the lithographic steps makes it difficult to enhance the productivity. It is therefore desired to work out a technique which enables small contact holes and a large trench to be formed in a fewer stages of processing.